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QPRO Family of XC1700D QML Serial Configuration PROMs
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February 8, 1999 (Version 2.0)
Product Specification
Features
* * * Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Serial Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices On-chip address counter, incremented by each rising edge on the clock input Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions The XQ1701L device is specified on a different datasheet. It supports the XQ4000EX/XL/XLA fast configuration mode (15.0 MHz). Low-power CMOS EPROM process Available in 5 V version only, the XQ1701L is available in 3.3V only Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages.
VCC VPP GND
Description
The XC1700D Hi-rel family of serial configuration PROMs (SPROMs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the SPROM. A short access time after the rising clock edge, data appears on the SPROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the SPROM. When the FPGA is in Slave Serial mode, the SPROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SPROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the FPGA design file into a standard HEX format which is then transferred to most commercial PROM programmers.
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* * * *
CE RESET/ OE or OE/ RESET CLK Address Counter TC
CEO
EPROM Cell Matrix
Output
OE DATA
X3185
Figure 1: Simplified Block Diagram (does not show programming circuit)
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Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low.
tion and severe problems in circuit debugging. Do not leave VPP floating!
VCC and GND
VCC is positive supply pin and GND is ground pin.
Serial PROM Pinouts
Pin Name DATA CLK 8-Pin 1 2 3 4 5 6 7 8
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGA's INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 programmer software. Third-party programmers have different methods to invert this pin.
RESET/OE (OE/RESET) CE GND CEO VPP VCC
Capacity
Device Configuration Bits XC1736D 36,288 XC1765D 65,536 XC17128D 131,072 XC17256D 262,144 XQ1701L 1,048,576 Note: The XQ1701L SPROMs are specified in a separate datasheet.
CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the next SPROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low.
Number of Configuration Bits, Including Header for Xilinx FPGAs and Compatible SPROMs
Device XC3000/A series XC4000 series XQ4005E XQ4010E XQ4013E XQ4025E XQ4013XL XQ4028EX XQ4036XL XQ4062XL Configuration Bits 14,819 to 94,984 95,008 to 247,968 95,008 178,144 247,968 422,176 393,632 668,184 832,528 1,433,864 SPROM XC1765D to XC17128D XC17128D to XC17256D XC17128D XC17256D XC17256D XQ1701L XQ1701L XQ1701L XQ1701L XQ1701L x 2
VPP
Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent opera-
Note: The XQ1701L SPROMs are specified in a separate
datasheet.
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QPROTM Family of XC1700D QML Serial Configuration PROMs
If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. Xilinx FPGAs take care of this automatically with an on-chip default pull-up resistor.
Controlling Serial PROMs
Connecting the FPGA device with the SPROM. * * * * The DATA output(s) of the SPROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the SPROM(s). The CEO output of a SPROM drives the CE input of the next SPROM in a daisy chain (if any). The RESET/OE input of all SPROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the SPROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods - such as driving RESET/OE from LDC or system reset - assume the SPROM internal power-on-reset is always in step with the FPGA's internal power-on-reset. This may not be a safe assumption. The SPROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. The CE input of the lead (or only) SPROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum.
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a SPROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the SPROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration.
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FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx SPROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the SPROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the SPROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK.
Cascading Serial Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded SPROMs provide additional memory. After the last bit from the first SPROM is read, the next clock signal to the SPROM asserts its CEO output Low and disables its DATA line. The second SPROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SPROMs are reset if the FPGA RESET pin goes Low, assuming the SPROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN.
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Vcc
DOUT
OPTIONAL Daisy-chained FPGAs with Different Configurations OPTIONAL Slave FPGAs with Identical Configurations Vcc
FPGA
MODES
RESET
RESET DIN CCLK DONE INIT VCC DATA CLK CE OE/RESET VPP DATA Cascaded Serial CE Memory OE/RESET CLK
SPROM CEO
(Low Resets the Address Pointer)
CCLK (OUTPUT)
DIN
DOUT (OUTPUT)
X8256_01
Figure 2: Master Serial Mode. The one-time-programmable SPROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the SPROM data output one CCLK cycle before the FPGA I/Os become active.
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Standby Mode
The SPROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address if address < TC: increment if address > TC: don't change Held reset Not changing Held reset Outputs DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby
Notes: 1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC+1 = address 0.
Important: Always tie the VPP pin to VCC in your application. Never leave VPP floating.
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XC1736D, XC1765D, XC17128D and XC17256D Absolute Maximum Ratings
Symbol VCC VPP VIN VTS TSTG TSOL Note: Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V C C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol VCC Note: Description Military Supply voltage relative to GND (TC = -55C to +125C) Min 4.50 Max 5.50 Units V
During normal read operation VPP must be connected to VCC
DC Characteristics Over Operating Condition
Symbol VIH VIL VOH VOL ICCA ICCS High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode XC17128D, XC17256D XC1736D, XC1765D IL CIN COUT Input or output leakage current Input Capacitance (VIN = GND, f = 1.0MHz) Sample tested Output Capacitance (VIN = GND, f = 1.0MHz) Sample tested -10.0 Military 0.4 10.0 50.0 1.5 10.0 10.0 10.0 V mA A mA A pF pF Description Min 2.0 0 3.7 Max VCC 0.8 Units V V V
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QPROTM Family of XC1700D QML Serial Configuration PROMs
AC Characteristics Over Operating Condition
CE 9 RESET/OE 11 THOE TLC 7 CLK TOE 2 DATA 4 TOH
X2634
TSCE
9 TSCE
10 THCE
8 THC
6 TCYC
1
3 TCAC
4 TOH
5 TDF
TCE
Symbol 1 2 3 4 5 6 7 8 9 10 11 TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE OE to Data Delay CE to Data Delay CLK to Data Delay
Description
XC1736D XC1765D Min Max 45 60 150 0 50 200 100 100 25 0 100
XC17128D XC17256D Min Max 25 45 50 0 50 80 20 20 20 0 20
Units ns ns ns ns ns ns ns ns ns ns ns
Data Hold From CE, OE, or CLK3 CE or OE to Data Float Delay2 & 3 Clock Periods CLK Low Time3 CLK High Time
3
CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLK (to guarantee proper counting) OE Hold Time (guarantees counters are reset)
Notes: 1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
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AC Characteristics Over Operating Condition When Cascading
RESET/OE
CE
CLK 12 TCDF DATA Last Bit 13 TOCK CEO 14 TOCE 14 TOCE
X3183
First Bit 15 TOOE
Symbol 12 13 14 15 TCDF TOCK TOCE TOOE
Description CLK to Data Float Delay2, 3 CLK to CEO Delay3 CE to CEO Delay3 RESET/OE to CEO Delay3
XC1736D XC1765D Min Max 50 65 45 40
XC17128D XC17256D Min Max 50 30 35 30
Units ns ns ns ns
Notes: 1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
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QPROTM Family of XC1700D QML Serial Configuration PROMs
Ordering Information XC17256D DD8
Device Number
XC1736D XC1765D XC17128D XC17256D
M
Operating Range/Processing
M = Military (TC = -55 to +125C) B = Military (TC = -55 to +125C) QML certified to MIL-PRF-38535
Package Type
DD8 = 8-Pin Ceramic DIP
Valid Ordering Combinations
XC17128DDD8M XC17256DDD8M 5962-9561701MPA XC1736DDD8M XC1765DDD8M 5962-9471701MPA XQ1701LCC44M XQ1701LSO20N
Note: The XQ1701L products are specified in the XC1700L High Density datasheet.
Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows.
17256D D
Device Number
XC1736D XC1765D XC17128D XC17256D
M
Operating Range/Processing
M = Military (TC = -55 to +125C) B = Military (TC = -55 to +125C) QML certified to MIL-PRF-38535
Package Type
D = 8-Pin Ceramic DIP
Revision Control
Date 2/8/99 Revision Removed the now obsolete Commercial and Industrial Grade part numbers and design support.
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